Regions of BJT Operation

Cut-off region: -

The transistor is off. There is no conduction between the collector and the emitter.(IB=0 therefore Ic=0)

Active region: -

The transistor is on. The collector current is proportional to and controlled by the base current (Ic=ßIB) and relatively insensitive to VCE. In this region the transistor can be an amplifier.

Saturation region: -

The transistor is on. The collector current varies very little with a change in the fill fully base current in the saturation region. The VCE is small, a few tenths of volt. The collector current is strongly dependent on VCE unlike in the active region. It is desirable to operate transistor switches in or near the saturation region when in their on state.

Rules for Bipolar Junction Transistors (BJTS)

1.For an npn transistor, the voltage at the collector VC must be greater than the voltage at the emitter VE by at least a few tenths of a volt; otherwise, current will not flow through the collector-emitter junction, no matter what the applied voltage at the base. For pnp transistors, the emitter voltage must be greater than the collector voltage by a similar amount.

2. For the npn transistor, there is a voltage drop from the base to the emitter of 0.6 V. For a pnp transistor, there is also a 0.6 V rise from the base to the emitter. In terms of operation, this means that the base voltage VB of an npn transistor must be at least 0.6 V greater that the emitter voltage VE; otherwise, the transistor will not pass emitter-to-collector current. For a pnp transistor, VB must be at least 0.6 V less than VE; otherwise, it will not pass collector-to-emitter current.

Basic Equations For The BJT

For npn: VB > VE + 0.6 V

For pnp: VBE – 0.6 V

For both npn and pnp anytime

IE = IC + IB

For both npn and pnp only in the active region

IC = h FE IB = ß IB

IE = IC+ IB = (ß+1) IB ~ ß IB

BJT Schematic Symbols

(Mnemonics for remembering the directions of the arrows are in parenthesis.)

Ohmmeters view of the BJT

Clearly a transistor cannot be made on the bench by combining two diodes. (Why is that?) Most ohmmeters not only measure resistance, but also measure the forward voltage drop across a diode. From this perspective you can identify the base and the type of transistor based on the following equivalent circuits.

Common Nomenclature (npn Example)

Types of Amplifiers

The transistor is a three terminal device, thus the input and the output must share one terminal in collector, common emitter, and common base.

Definition of Gain

Gain is defined as the ratio of the output signal to the input signal. Because transistor amplifiers often have a quiescent output (a non zero output when the input is zero) we define gain as the derivative of the output with respect to the input. Thus gain is defined as the ratio of the change in output to the change in input.

So far we have not specified the output quantity, the reason is that we can define the gain with respect to any given output and input quantity.

General definition: A =d(Output) / d(Input) if (Output) = 0 when (Input) = 0, then A = (Output) / (Input)

Voltage Gain: A_v = dV_out/ dV_in if V_out = 0 when V_in = 0, then A = V_out / V_in

Current Gain: A_I = dI_out / dI_in if I_out = 0 when I_in = 0, then A = I_out / I_in

Power Gain: A_p = dP_out / dP_in if P_out = 0 when P_in = 0, then A = P_out / P_in

Note that a negative gain means that the sign of the signal is inverted. Negative gain is not possible for Power Gain. |A| less than unity indicate that the output is smaller than the input.

The quantities need not be the same. If the input and output quantities are different, the gain is no longer unitless. The most common examples are transimpedancc gain and transadmittancc gain.

Transmpedancc Gain: A_Z = dV_out / dI_in if V_out = 0 when I_in = 0, then I = I_out / I_in

Transadmittancc Gain: A_Y = dI_out / dV_in if I_out = 0 when V_in = 0, then A = I_out / I_in

Input Impedance of a Transistor

Impedance is defined as Z = V/I. In linear circuits (with resistors, capacitors, inductors, batteries, etc.) this ratio is the reciprocal of the slope of the I versus V graph. In circuits with nonlinear elements such as a transistor, the input impedance of the resistor is defined as the reciprocal of the slope of the I versus V graph. This is simply the derivative of V_in with respect to I_in-

Z_in = dV_in / dI_in

We can easily find Z_in from what we know already of the behavior of the transistor. We know that the sum of V_BE and the IR drop across R_E must equal V_in.

V_in = V_B = V_BE +V_E = V_BE + I_ER_E [I_R = I_C + I_B = βI_B + I_B = (β + 1)I_B]

V_in =V_BE + I_ER_E = I_B(β + 1)R_E [I_B = I_in]

V_in = V_BE + I_in (β + 1) R_E

Taking the derivative of V_in with respect to I_in, remembering that V_BE is a constant, we get the result:

Z_in = dV_in/dI_in = d/dI_in(V_BE + I_in (β + 1)R_E) = (β + 1)R_E

Zin = (β + 1)RE ≈ βRE

Because I_E = I_B (β + 1). The IR drop across R_E is greater then it would be for I_B alone. The amplification of the base current causes R_E to appear larger to a source looking into the input by (β + 1).

Output Impedance of a Transistor for the Emitter Follower (Common Collector)

The output impedance seen by the load (R_E in this example) is defined as:

Z_out = - dV_out / dI_out

The minus sign in the derivative comes from the fact the output impedance has the effect of decreasing V_out. The output current I_E, which is related to the base current.

V_in = I_BR_S + V_BE +V_E [V_out = V_E]

V_out = V_E = V_in – I_BR_S – V_BE [I_out = I_E and I_B = I_E/(β + 1)]

V_out = V_in – {I_E/(β + 1)}R_S – V_BE = V_in – {I_out/( β + 1)}R_S – V_BE

= - I_out{R_S/(β + 1)} + (V_in – V_BE)

So, Z_out = - dV_out/dI_out = -d/dI_out [ - I_out{R_S/(β + 1)} + (V_in – V_BE) ]

Z_out = R_S/(β + 1)

Thus we obtain the result that the impedance of the source, as viewed by the load, is reduced by the factor ~ 1/ β.

Zout = {RS/( β + 1) ≈ RS/β

Definition of Field effect Transistor (FET) and FET Schematic Symbols

The Field effect Transistor (FET) is an active device. In simple terms, it is a voltage controlled valve. The gate-source voltage (VGS) controls the drain current (ID).

The FET is a three terminal device like the BJT, but operates by a different principle. The three terminals are called the source, drain and gate. The voltage applied to the gate controls the current flowing in the source-drain channel. Because no current flows through the gate, the input impedance of the FET is extremely large (in the range of 10¹⁰ - 10¹⁵ Ω). The large input impedance of the FET makes them an excellent choice for amplifier inputs.

The two common families of FETs, the junction FET (JFET) and the metal oxide semiconductor FET (MOSFET) differ in the way the gate contact is made on the source-drain channel.

FET Schematic Symbols: -

Two Versions of the symbols are in common use. The symbols in the top row depict the source and drain as being symmetric. This is not generally true. Slight asymmetries are built into the channel during manufacturing which optimize the performance of the FET. Thus it is necessary to distinguish the source from the drain. In this class we will use the asymmetric symbols found on the bottom row, which depict the gate nearly opposite the source. The designation n-channel means that the channel is n doped and the gate is p doped. The p-channel is complement of n-channel.

Regions of JFET operation

Cut-off Region:

The transistor is off. There is no conduction between the drain and the source when the gate-source voltage is greater than the cut-off voltage (ID = 0 for VGS > VGSoff)

Active Region (also called the Saturation Region):

The transistor is on. The drain current is controlled by the gate-source voltage (VGS) and relatively insensitive to VDS. In this region the transistor can be an amplifier.

In the active Region ID = IDSS (1 – VGS / VGSoff) 2

Ohmic Region:

The transistor is on, but behaves as a voltage proportional to the source-drain voltage and is controlled by the gate voltage.

ID = IDSS [ 2 (1 – VGS / VGSoff) VDS / - VGSoff - (VDS / VGSoff) 2 ]

In the Ohmic Region: RDS ≈ VGSoff / 2IDSS (VGS - VGSoff) = 1 / gm

Common Circuit Application(Voltage Controlled Switch)

For the on state the gate voltage V_GS = 0 and for the off state |V_GS| > |V_GS.off| (of greater magnitude then V_GS.off and with the same sign). The sign of the voltage depends on the type of FET, negative for n-channel and positive for p-channel.

Common Circuit Application(Current source)

The drain current is set by R_S such that V_GS = I_DR_S. Any value of current can be chosen between zero and I_DSS

Common Circuit Application(Source Follower)

The simple source follower is shown below. The improved version is shown at the right. The lower JFET forms a current source. The result is that V_GS is held constant, removing the defects of the simple circuit.

Common Circuit Application(Voltage-Controlled Resistor)

V_GS must be between zero and V_GS.off .

Common Circuit Application(JFET Diode)

The JFET pn gate junction can be used as a diode by connecting the source and the drain terminals. This is done if very low reverse leakage currents are required. The leakage current is very low because the reverse leakage current scales with the gate area. Small gate areas are designed into JFETs because it decreases the gate-source and the gate-drain capacitances.

Metal–oxide–semiconductor structure

A traditional metal–oxide–semiconductor (MOS) structure is obtained by depositing a layer of silicon dioxide (SiO₂) and a layer of metal (polycrystalline silicon is commonly used instead of metal) on top of a semiconductor die. As the silicon dioxide is a dielectric material its structure is equivalent to a planar capacitor, with one of the electrodes replaced by a semiconductor.

When a voltage is applied across a MOS structure, it modifies the distribution of charges in the semiconductor. If we consider a P-type semiconductor (with N_A the density of acceptors, p the density of holes; p = N_A in neutral bulk), a positive voltage, V_GB, from gate to body (see figure) creates a depletion layer by forcing the positively charged holes away from the gate-insulator/semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions. See doping (semiconductor). If V_GB is high enough, a high concentration of negative charge carriers forms in an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator. (Unlike the MOSFET, discussed below, where the inversion layer electrons are supplied rapidly from the source/drain electrodes, in the MOS capacitor they are produced much more slowly by thermal generation through carrier generation and recombination centers in the depletion region.) Conventionally, the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage.

This structure with P-type body is the basis of the N-type MOSFET, which requires the addition of an N-type source and drain regions.

From: - Wikipedia Encyclopedia

NMOS logic

NMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. nMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).

The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage, while a resistor is placed between the logic gate output and the positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be active, creating a current path between the negative supply and the output.

As an example, here is a NOR gate in NMOS logic. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low (logic 0, = False). When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which occurs only when both A and B are low, thus satisfying the truth table of a NOR gate:

A	B	A NOR B
0	0	1
0	1	0
1	0	0
1	1	0

While NMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with NMOSFETs), it has several shortcomings as well. The worst problem is that a DC current flows through an NMOS logic gate when the PDN is active, that is whenever the output is low. This leads to static power dissipation even when the circuit sits idle.

Also, NMOS circuits are slow to transition from low to high. When transitioning from high to low, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the positive supply rail is much greater, so the low to high transition takes longer. Using a resistor of lower value will speed up the process but also increases static power dissipation.

From: - Wikipedia encyclopedia

PMOS logic

PMOS logic uses p-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. pMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).

The p-type MOSFETs are arranged in a so-called "pull-up network" (PUN) between the logic gate output and positive supply voltage, while a resistor is placed between the logic gate output and the negative supply voltage. The circuit is designed such that if the desired output is high, then the PUN will be active, creating a current path between the positive supply and the output.

While pMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with pMOSFETs), it has several shortcomings as well. The worst problem is that a DC current flows through a pMOS logic gate when the PUN is active, that is whenever the output is high. This leads to static power dissipation even when the circuit sits idle.

Also, pMOS circuits are slow to transition from high to low. When transitioning from low to high, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the negative supply rail is much greater, so the high to low transition takes longer. Using a resistor of lower value will speed up the process but also increases static power dissipation.

From: - Wikipedia encyclopedia